Sector Processor (SP05) Design
This is a complementary page to the CSC Track-Finder main page.
It provides details on the CSC Sector Processor design.
Sector Processor Schematics, pre-production version (2004)
Sector Processor Schematics, production version (2005)
SP Mezzanine Card Schematics (SP core FPGA)
SP Daughter Board Schematics (QPLL board)
SP Transition Board Schematics (CSC ó DT interface)
DDU Extender Board Schematics (for DDU in the TF crate)
Version July 1, 2006: (VM, FA, DD, SP: readjusted FC_CMD timing, SP: added delay for CSC stubs in SP_FPGA)
	SP05 Registers
	SP05 Readout Format
	SP05 svf file for chain0
	SP05 svf file for chain1
Version August 1, 2006: (FA, SP: fixed DT quality bits mapping, DD: inserted 4 idles between events, VM: added CSR_REQ to delay L1req)
	SP05 svf file for chain0
	SP05 svf file for chain1
Trial Version January 09, 2007: (FA, VM: same as of Aug, 1, DD: data coded LSB first, CRC reversed bit order)
	SP05 svf file for chain1
Version March 17, 2007: (FA: same as of Aug 01, 2006; DD: same as of Jan 09, 2007; VM: CSR_FMM control added)
	SP05 svf file for chain1
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Last modified March 17, 2007 by Lev Uvarov